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RP2040 OLED SSD1306
Driver/Exemplos para display OLED SSD1306 no RP2040
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| #define M33_ACTLR_DISFOLD_ACCESS "RW" |
| #define M33_ACTLR_DISITMATBFLUSH_ACCESS "RW" |
| #define M33_ACTLR_DISMCYCINT_ACCESS "RW" |
| #define M33_ACTLR_DISOOFP_ACCESS "RW" |
| #define M33_ACTLR_EXTEXCLALL_ACCESS "RW" |
| #define M33_ACTLR_FPEXCODIS_ACCESS "RW" |
| #define M33_AIRCR_BFHFNMINS_ACCESS "RW" |
| #define M33_AIRCR_ENDIANESS_ACCESS "RO" |
| #define M33_AIRCR_PRIGROUP_ACCESS "RW" |
| #define M33_AIRCR_PRIS_ACCESS "RW" |
| #define M33_AIRCR_SYSRESETREQ_ACCESS "RW" |
| #define M33_AIRCR_SYSRESETREQS_ACCESS "RW" |
| #define M33_AIRCR_VECTCLRACTIVE_ACCESS "RW" |
| #define M33_AIRCR_VECTKEY_ACCESS "RW" |
| #define M33_ASICCTL_ACCESS "RW" |
| #define M33_BFAR_ADDRESS_ACCESS "RW" |
| #define M33_CCR_BFHFNMIGN_ACCESS "RW" |
| #define M33_CCR_BP_ACCESS "RO" |
| #define M33_CCR_DC_ACCESS "RO" |
| #define M33_CCR_DIV_0_TRP_ACCESS "RW" |
| #define M33_CCR_IC_ACCESS "RO" |
| #define M33_CCR_RES1_1_ACCESS "RO" |
| #define M33_CCR_RES1_ACCESS "RO" |
| #define M33_CCR_STKOFHFNMIGN_ACCESS "RW" |
| #define M33_CCR_UNALIGN_TRP_ACCESS "RW" |
| #define M33_CCR_USERSETMPEND_ACCESS "RW" |
| #define M33_CFSR_BFSR_BFARVALID_ACCESS "RW" |
| #define M33_CFSR_BFSR_IBUSERR_ACCESS "RW" |
| #define M33_CFSR_BFSR_IMPRECISERR_ACCESS "RW" |
| #define M33_CFSR_BFSR_LSPERR_ACCESS "RW" |
| #define M33_CFSR_BFSR_PRECISERR_ACCESS "RW" |
| #define M33_CFSR_BFSR_STKERR_ACCESS "RW" |
| #define M33_CFSR_BFSR_UNSTKERR_ACCESS "RW" |
| #define M33_CFSR_MMFSR_ACCESS "RW" |
| #define M33_CFSR_UFSR_DIVBYZERO_ACCESS "RW" |
| #define M33_CFSR_UFSR_INVPC_ACCESS "RW" |
| #define M33_CFSR_UFSR_INVSTATE_ACCESS "RW" |
| #define M33_CFSR_UFSR_NOCP_ACCESS "RW" |
| #define M33_CFSR_UFSR_STKOF_ACCESS "RW" |
| #define M33_CFSR_UFSR_UNALIGNED_ACCESS "RW" |
| #define M33_CFSR_UFSR_UNDEFINSTR_ACCESS "RW" |
| #define M33_CIDR0_PRMBL_0_ACCESS "RO" |
| #define M33_CIDR1_CLASS_ACCESS "RO" |
| #define M33_CIDR1_PRMBL_1_ACCESS "RO" |
| #define M33_CIDR2_PRMBL_2_ACCESS "RO" |
| #define M33_CIDR3_PRMBL_3_ACCESS "RO" |
| #define M33_CPACR_CP0_ACCESS "RW" |
| #define M33_CPACR_CP10_ACCESS "RW" |
| #define M33_CPACR_CP11_ACCESS "RW" |
| #define M33_CPACR_CP1_ACCESS "RW" |
| #define M33_CPACR_CP2_ACCESS "RW" |
| #define M33_CPACR_CP3_ACCESS "RW" |
| #define M33_CPACR_CP4_ACCESS "RW" |
| #define M33_CPACR_CP5_ACCESS "RW" |
| #define M33_CPACR_CP6_ACCESS "RW" |
| #define M33_CPACR_CP7_ACCESS "RW" |
| #define M33_CPUID_ARCHITECTURE_ACCESS "RO" |
| #define M33_CPUID_IMPLEMENTER_ACCESS "RO" |
| #define M33_CPUID_PARTNO_ACCESS "RO" |
| #define M33_CPUID_REVISION_ACCESS "RO" |
| #define M33_CPUID_VARIANT_ACCESS "RO" |
| #define M33_CTIAPPCLEAR_APPCLEAR_ACCESS "RW" |
| #define M33_CTIAPPPULSE_APPULSE_ACCESS "RW" |
| #define M33_CTIAPPSET_APPSET_ACCESS "RW" |
| #define M33_CTICHINSTATUS_CTICHOUTSTATUS_ACCESS "RO" |
| #define M33_CTICONTROL_GLBEN_ACCESS "RW" |
| #define M33_CTIGATE_CTIGATEEN0_ACCESS "RW" |
| #define M33_CTIGATE_CTIGATEEN1_ACCESS "RW" |
| #define M33_CTIGATE_CTIGATEEN2_ACCESS "RW" |
| #define M33_CTIGATE_CTIGATEEN3_ACCESS "RW" |
| #define M33_CTIINEN0_TRIGINEN_ACCESS "RW" |
| #define M33_CTIINEN1_TRIGINEN_ACCESS "RW" |
| #define M33_CTIINEN2_TRIGINEN_ACCESS "RW" |
| #define M33_CTIINEN3_TRIGINEN_ACCESS "RW" |
| #define M33_CTIINEN4_TRIGINEN_ACCESS "RW" |
| #define M33_CTIINEN5_TRIGINEN_ACCESS "RW" |
| #define M33_CTIINEN6_TRIGINEN_ACCESS "RW" |
| #define M33_CTIINEN7_TRIGINEN_ACCESS "RW" |
| #define M33_CTIINTACK_INTACK_ACCESS "RW" |
| #define M33_CTIOUTEN0_TRIGOUTEN_ACCESS "RW" |
| #define M33_CTIOUTEN1_TRIGOUTEN_ACCESS "RW" |
| #define M33_CTIOUTEN2_TRIGOUTEN_ACCESS "RW" |
| #define M33_CTIOUTEN3_TRIGOUTEN_ACCESS "RW" |
| #define M33_CTIOUTEN4_TRIGOUTEN_ACCESS "RW" |
| #define M33_CTIOUTEN5_TRIGOUTEN_ACCESS "RW" |
| #define M33_CTIOUTEN6_TRIGOUTEN_ACCESS "RW" |
| #define M33_CTIOUTEN7_TRIGOUTEN_ACCESS "RW" |
| #define M33_CTITRIGINSTATUS_TRIGINSTATUS_ACCESS "RO" |
| #define M33_CTITRIGOUTSTATUS_TRIGOUTSTATUS_ACCESS "RO" |
| #define M33_CTR_CWG_ACCESS "RO" |
| #define M33_CTR_DMINLINE_ACCESS "RO" |
| #define M33_CTR_ERG_ACCESS "RO" |
| #define M33_CTR_IMINLINE_ACCESS "RO" |
| #define M33_CTR_RES1_1_ACCESS "RO" |
| #define M33_CTR_RES1_ACCESS "RO" |
| #define M33_DCIDR0_PRMBL_0_ACCESS "RO" |
| #define M33_DCIDR1_CLASS_ACCESS "RO" |
| #define M33_DCIDR1_PRMBL_1_ACCESS "RO" |
| #define M33_DCIDR2_PRMBL_2_ACCESS "RO" |
| #define M33_DCIDR3_PRMBL_3_ACCESS "RO" |
| #define M33_DCRDR_DBGTMP_ACCESS "RW" |
| #define M33_DCRSR_REGSEL_ACCESS "RW" |
| #define M33_DCRSR_REGWNR_ACCESS "RW" |
| #define M33_DDEVARCH_ARCHITECT_ACCESS "RO" |
| #define M33_DDEVARCH_ARCHPART_ACCESS "RO" |
| #define M33_DDEVARCH_ARCHVER_ACCESS "RO" |
| #define M33_DDEVARCH_PRESENT_ACCESS "RO" |
| #define M33_DDEVARCH_REVISION_ACCESS "RO" |
| #define M33_DDEVTYPE_MAJOR_ACCESS "RO" |
| #define M33_DDEVTYPE_SUB_ACCESS "RO" |
| #define M33_DEMCR_MON_EN_ACCESS "RW" |
| #define M33_DEMCR_MON_PEND_ACCESS "RW" |
| #define M33_DEMCR_MON_REQ_ACCESS "RW" |
| #define M33_DEMCR_MON_STEP_ACCESS "RW" |
| #define M33_DEMCR_SDME_ACCESS "RO" |
| #define M33_DEMCR_TRCENA_ACCESS "RW" |
| #define M33_DEMCR_VC_BUSERR_ACCESS "RW" |
| #define M33_DEMCR_VC_CHKERR_ACCESS "RW" |
| #define M33_DEMCR_VC_CORERESET_ACCESS "RW" |
| #define M33_DEMCR_VC_HARDERR_ACCESS "RW" |
| #define M33_DEMCR_VC_INTERR_ACCESS "RW" |
| #define M33_DEMCR_VC_MMERR_ACCESS "RW" |
| #define M33_DEMCR_VC_NOCPERR_ACCESS "RW" |
| #define M33_DEMCR_VC_SFERR_ACCESS "RW" |
| #define M33_DEMCR_VC_STATERR_ACCESS "RW" |
| #define M33_DEVARCH_ARCHID_ACCESS "RO" |
| #define M33_DEVARCH_ARCHITECT_ACCESS "RO" |
| #define M33_DEVARCH_PRESENT_ACCESS "RO" |
| #define M33_DEVARCH_REVISION_ACCESS "RO" |
| #define M33_DEVID_EXTMUXNUM_ACCESS "RO" |
| #define M33_DEVID_NUMCH_ACCESS "RO" |
| #define M33_DEVID_NUMTRIG_ACCESS "RO" |
| #define M33_DEVTYPE_MAJOR_ACCESS "RO" |
| #define M33_DEVTYPE_SUB_ACCESS "RO" |
| #define M33_DFSR_BKPT_ACCESS "RW" |
| #define M33_DFSR_DWTTRAP_ACCESS "RW" |
| #define M33_DFSR_EXTERNAL_ACCESS "RW" |
| #define M33_DFSR_HALTED_ACCESS "RW" |
| #define M33_DFSR_VCATCH_ACCESS "RW" |
| #define M33_DHCSR_C_DEBUGEN_ACCESS "RW" |
| #define M33_DHCSR_C_HALT_ACCESS "RW" |
| #define M33_DHCSR_C_MASKINTS_ACCESS "RW" |
| #define M33_DHCSR_C_SNAPSTALL_ACCESS "RW" |
| #define M33_DHCSR_C_STEP_ACCESS "RW" |
| #define M33_DHCSR_S_HALT_ACCESS "RO" |
| #define M33_DHCSR_S_LOCKUP_ACCESS "RO" |
| #define M33_DHCSR_S_REGRDY_ACCESS "RO" |
| #define M33_DHCSR_S_RESET_ST_ACCESS "RO" |
| #define M33_DHCSR_S_RESTART_ST_ACCESS "RO" |
| #define M33_DHCSR_S_RETIRE_ST_ACCESS "RO" |
| #define M33_DHCSR_S_SDE_ACCESS "RO" |
| #define M33_DHCSR_S_SLEEP_ACCESS "RO" |
| #define M33_DPIDR0_PART_0_ACCESS "RO" |
| #define M33_DPIDR1_DES_0_ACCESS "RO" |
| #define M33_DPIDR1_PART_1_ACCESS "RO" |
| #define M33_DPIDR2_DES_1_ACCESS "RO" |
| #define M33_DPIDR2_JEDEC_ACCESS "RO" |
| #define M33_DPIDR2_REVISION_ACCESS "RO" |
| #define M33_DPIDR3_CMOD_ACCESS "RO" |
| #define M33_DPIDR3_REVAND_ACCESS "RO" |
| #define M33_DPIDR4_DES_2_ACCESS "RO" |
| #define M33_DPIDR4_SIZE_ACCESS "RO" |
| #define M33_DPIDR5_ACCESS "RW" |
| #define M33_DPIDR6_ACCESS "RW" |
| #define M33_DPIDR7_ACCESS "RW" |
| #define M33_DSCSR_CDS_ACCESS "RW" |
| #define M33_DSCSR_CDSKEY_ACCESS "RW" |
| #define M33_DSCSR_SBRSEL_ACCESS "RW" |
| #define M33_DSCSR_SBRSELEN_ACCESS "RW" |
| #define M33_DWT_CIDR0_PRMBL_0_ACCESS "RO" |
| #define M33_DWT_CIDR1_CLASS_ACCESS "RO" |
| #define M33_DWT_CIDR1_PRMBL_1_ACCESS "RO" |
| #define M33_DWT_CIDR2_PRMBL_2_ACCESS "RO" |
| #define M33_DWT_CIDR3_PRMBL_3_ACCESS "RO" |
| #define M33_DWT_COMP0_ACCESS "RW" |
| #define M33_DWT_COMP1_ACCESS "RW" |
| #define M33_DWT_COMP2_ACCESS "RW" |
| #define M33_DWT_COMP3_ACCESS "RW" |
| #define M33_DWT_CTRL_CPIEVTENA_ACCESS "RW" |
| #define M33_DWT_CTRL_CYCCNTENA_ACCESS "RW" |
| #define M33_DWT_CTRL_CYCDISS_ACCESS "RW" |
| #define M33_DWT_CTRL_CYCEVTENA_ACCESS "RW" |
| #define M33_DWT_CTRL_CYCTAP_ACCESS "RW" |
| #define M33_DWT_CTRL_EXCEVTENA_ACCESS "RW" |
| #define M33_DWT_CTRL_EXTTRCENA_ACCESS "RW" |
| #define M33_DWT_CTRL_FOLDEVTENA_ACCESS "RW" |
| #define M33_DWT_CTRL_LSUEVTENA_ACCESS "RW" |
| #define M33_DWT_CTRL_NOCYCCNT_ACCESS "RO" |
| #define M33_DWT_CTRL_NOEXTTRIG_ACCESS "RO" |
| #define M33_DWT_CTRL_NOPRFCNT_ACCESS "RO" |
| #define M33_DWT_CTRL_NOTRCPKT_ACCESS "RO" |
| #define M33_DWT_CTRL_NUMCOMP_ACCESS "RO" |
| #define M33_DWT_CTRL_PCSAMPLENA_ACCESS "RW" |
| #define M33_DWT_CTRL_POSTINIT_ACCESS "RW" |
| #define M33_DWT_CTRL_POSTPRESET_ACCESS "RW" |
| #define M33_DWT_CTRL_SLEEPEVTENA_ACCESS "RW" |
| #define M33_DWT_CTRL_SYNCTAP_ACCESS "RW" |
| #define M33_DWT_CYCCNT_CYCCNT_ACCESS "RW" |
| #define M33_DWT_DEVARCH_ARCHITECT_ACCESS "RO" |
| #define M33_DWT_DEVARCH_ARCHPART_ACCESS "RO" |
| #define M33_DWT_DEVARCH_ARCHVER_ACCESS "RO" |
| #define M33_DWT_DEVARCH_PRESENT_ACCESS "RO" |
| #define M33_DWT_DEVARCH_REVISION_ACCESS "RO" |
| #define M33_DWT_DEVTYPE_MAJOR_ACCESS "RO" |
| #define M33_DWT_DEVTYPE_SUB_ACCESS "RO" |
| #define M33_DWT_EXCCNT_EXCCNT_ACCESS "RW" |
| #define M33_DWT_FOLDCNT_FOLDCNT_ACCESS "RW" |
| #define M33_DWT_FUNCTION0_ACTION_ACCESS "RW" |
| #define M33_DWT_FUNCTION0_DATAVSIZE_ACCESS "RW" |
| #define M33_DWT_FUNCTION0_ID_ACCESS "RO" |
| #define M33_DWT_FUNCTION0_MATCH_ACCESS "RW" |
| #define M33_DWT_FUNCTION0_MATCHED_ACCESS "RO" |
| #define M33_DWT_FUNCTION1_ACTION_ACCESS "RW" |
| #define M33_DWT_FUNCTION1_DATAVSIZE_ACCESS "RW" |
| #define M33_DWT_FUNCTION1_ID_ACCESS "RO" |
| #define M33_DWT_FUNCTION1_MATCH_ACCESS "RW" |
| #define M33_DWT_FUNCTION1_MATCHED_ACCESS "RO" |
| #define M33_DWT_FUNCTION2_ACTION_ACCESS "RW" |
| #define M33_DWT_FUNCTION2_DATAVSIZE_ACCESS "RW" |
| #define M33_DWT_FUNCTION2_ID_ACCESS "RO" |
| #define M33_DWT_FUNCTION2_MATCH_ACCESS "RW" |
| #define M33_DWT_FUNCTION2_MATCHED_ACCESS "RO" |
| #define M33_DWT_FUNCTION3_ACTION_ACCESS "RW" |
| #define M33_DWT_FUNCTION3_DATAVSIZE_ACCESS "RW" |
| #define M33_DWT_FUNCTION3_ID_ACCESS "RO" |
| #define M33_DWT_FUNCTION3_MATCH_ACCESS "RW" |
| #define M33_DWT_FUNCTION3_MATCHED_ACCESS "RO" |
| #define M33_DWT_LSUCNT_LSUCNT_ACCESS "RW" |
| #define M33_DWT_PIDR0_PART_0_ACCESS "RO" |
| #define M33_DWT_PIDR1_DES_0_ACCESS "RO" |
| #define M33_DWT_PIDR1_PART_1_ACCESS "RO" |
| #define M33_DWT_PIDR2_DES_1_ACCESS "RO" |
| #define M33_DWT_PIDR2_JEDEC_ACCESS "RO" |
| #define M33_DWT_PIDR2_REVISION_ACCESS "RO" |
| #define M33_DWT_PIDR3_CMOD_ACCESS "RO" |
| #define M33_DWT_PIDR3_REVAND_ACCESS "RO" |
| #define M33_DWT_PIDR4_DES_2_ACCESS "RO" |
| #define M33_DWT_PIDR4_SIZE_ACCESS "RO" |
| #define M33_DWT_PIDR5_ACCESS "RW" |
| #define M33_DWT_PIDR6_ACCESS "RW" |
| #define M33_DWT_PIDR7_ACCESS "RW" |
| #define M33_FP_CIDR0_PRMBL_0_ACCESS "RO" |
| #define M33_FP_CIDR1_CLASS_ACCESS "RO" |
| #define M33_FP_CIDR1_PRMBL_1_ACCESS "RO" |
| #define M33_FP_CIDR2_PRMBL_2_ACCESS "RO" |
| #define M33_FP_CIDR3_PRMBL_3_ACCESS "RO" |
| #define M33_FP_COMP0_BE_ACCESS "RW" |
| #define M33_FP_COMP1_BE_ACCESS "RW" |
| #define M33_FP_COMP2_BE_ACCESS "RW" |
| #define M33_FP_COMP3_BE_ACCESS "RW" |
| #define M33_FP_COMP4_BE_ACCESS "RW" |
| #define M33_FP_COMP5_BE_ACCESS "RW" |
| #define M33_FP_COMP6_BE_ACCESS "RW" |
| #define M33_FP_COMP7_BE_ACCESS "RW" |
| #define M33_FP_CTRL_ENABLE_ACCESS "RW" |
| #define M33_FP_CTRL_KEY_ACCESS "RW" |
| #define M33_FP_CTRL_NUM_CODE_14_12__ACCESS "RO" |
| #define M33_FP_CTRL_NUM_CODE_7_4__ACCESS "RO" |
| #define M33_FP_CTRL_NUM_LIT_ACCESS "RO" |
| #define M33_FP_CTRL_REV_ACCESS "RO" |
| #define M33_FP_DEVARCH_ARCHITECT_ACCESS "RO" |
| #define M33_FP_DEVARCH_ARCHPART_ACCESS "RO" |
| #define M33_FP_DEVARCH_ARCHVER_ACCESS "RO" |
| #define M33_FP_DEVARCH_PRESENT_ACCESS "RO" |
| #define M33_FP_DEVARCH_REVISION_ACCESS "RO" |
| #define M33_FP_DEVTYPE_MAJOR_ACCESS "RO" |
| #define M33_FP_DEVTYPE_SUB_ACCESS "RO" |
| #define M33_FP_PIDR0_PART_0_ACCESS "RO" |
| #define M33_FP_PIDR1_DES_0_ACCESS "RO" |
| #define M33_FP_PIDR1_PART_1_ACCESS "RO" |
| #define M33_FP_PIDR2_DES_1_ACCESS "RO" |
| #define M33_FP_PIDR2_JEDEC_ACCESS "RO" |
| #define M33_FP_PIDR2_REVISION_ACCESS "RO" |
| #define M33_FP_PIDR3_CMOD_ACCESS "RO" |
| #define M33_FP_PIDR3_REVAND_ACCESS "RO" |
| #define M33_FP_PIDR4_DES_2_ACCESS "RO" |
| #define M33_FP_PIDR4_SIZE_ACCESS "RO" |
| #define M33_FP_PIDR5_ACCESS "RW" |
| #define M33_FP_PIDR6_ACCESS "RW" |
| #define M33_FP_PIDR7_ACCESS "RW" |
| #define M33_FP_REMAP_REMAP_ACCESS "RO" |
| #define M33_FP_REMAP_RMPSPT_ACCESS "RO" |
| #define M33_FPCAR_ADDRESS_ACCESS "RW" |
| #define M33_FPCCR_ASPEN_ACCESS "RW" |
| #define M33_FPCCR_BFRDY_ACCESS "RW" |
| #define M33_FPCCR_CLRONRET_ACCESS "RW" |
| #define M33_FPCCR_CLRONRETS_ACCESS "RW" |
| #define M33_FPCCR_HFRDY_ACCESS "RW" |
| #define M33_FPCCR_LSPACT_ACCESS "RW" |
| #define M33_FPCCR_LSPEN_ACCESS "RW" |
| #define M33_FPCCR_LSPENS_ACCESS "RW" |
| #define M33_FPCCR_MMRDY_ACCESS "RW" |
| #define M33_FPCCR_MONRDY_ACCESS "RW" |
| #define M33_FPCCR_S_ACCESS "RW" |
| #define M33_FPCCR_SFRDY_ACCESS "RW" |
| #define M33_FPCCR_SPLIMVIOL_ACCESS "RW" |
| #define M33_FPCCR_THREAD_ACCESS "RW" |
| #define M33_FPCCR_TS_ACCESS "RW" |
| #define M33_FPCCR_UFRDY_ACCESS "RW" |
| #define M33_FPCCR_USER_ACCESS "RW" |
| #define M33_FPDSCR_AHP_ACCESS "RW" |
| #define M33_FPDSCR_DN_ACCESS "RW" |
| #define M33_FPDSCR_FZ_ACCESS "RW" |
| #define M33_FPDSCR_RMODE_ACCESS "RW" |
| #define M33_HFSR_DEBUGEVT_ACCESS "RW" |
| #define M33_HFSR_FORCED_ACCESS "RW" |
| #define M33_HFSR_VECTTBL_ACCESS "RW" |
| #define M33_ICSR_ISRPENDING_ACCESS "RO" |
| #define M33_ICSR_ISRPREEMPT_ACCESS "RO" |
| #define M33_ICSR_PENDNMICLR_ACCESS "RW" |
| #define M33_ICSR_PENDNMISET_ACCESS "RO" |
| #define M33_ICSR_PENDSTCLR_ACCESS "RW" |
| #define M33_ICSR_PENDSTSET_ACCESS "RO" |
| #define M33_ICSR_PENDSVCLR_ACCESS "RW" |
| #define M33_ICSR_PENDSVSET_ACCESS "RO" |
| #define M33_ICSR_RETTOBASE_ACCESS "RO" |
| #define M33_ICSR_STTNS_ACCESS "RW" |
| #define M33_ICSR_VECTACTIVE_ACCESS "RO" |
| #define M33_ICSR_VECTPENDING_ACCESS "RO" |
| #define M33_ICTR_INTLINESNUM_ACCESS "RO" |
| #define M33_ID_AFR0_IMPDEF0_ACCESS "RO" |
| #define M33_ID_AFR0_IMPDEF1_ACCESS "RO" |
| #define M33_ID_AFR0_IMPDEF2_ACCESS "RO" |
| #define M33_ID_AFR0_IMPDEF3_ACCESS "RO" |
| #define M33_ID_DFR0_MPROFDBG_ACCESS "RO" |
| #define M33_ID_ISAR0_BITCOUNT_ACCESS "RO" |
| #define M33_ID_ISAR0_BITFIELD_ACCESS "RO" |
| #define M33_ID_ISAR0_CMPBRANCH_ACCESS "RO" |
| #define M33_ID_ISAR0_COPROC_ACCESS "RO" |
| #define M33_ID_ISAR0_DEBUG_ACCESS "RO" |
| #define M33_ID_ISAR0_DIVIDE_ACCESS "RO" |
| #define M33_ID_ISAR1_EXTEND_ACCESS "RO" |
| #define M33_ID_ISAR1_IFTHEN_ACCESS "RO" |
| #define M33_ID_ISAR1_IMMEDIATE_ACCESS "RO" |
| #define M33_ID_ISAR1_INTERWORK_ACCESS "RO" |
| #define M33_ID_ISAR2_LOADSTORE_ACCESS "RO" |
| #define M33_ID_ISAR2_MEMHINT_ACCESS "RO" |
| #define M33_ID_ISAR2_MULT_ACCESS "RO" |
| #define M33_ID_ISAR2_MULTIACCESSINT_ACCESS "RO" |
| #define M33_ID_ISAR2_MULTS_ACCESS "RO" |
| #define M33_ID_ISAR2_MULTU_ACCESS "RO" |
| #define M33_ID_ISAR2_REVERSAL_ACCESS "RO" |
| #define M33_ID_ISAR3_SATURATE_ACCESS "RO" |
| #define M33_ID_ISAR3_SIMD_ACCESS "RO" |
| #define M33_ID_ISAR3_SVC_ACCESS "RO" |
| #define M33_ID_ISAR3_SYNCHPRIM_ACCESS "RO" |
| #define M33_ID_ISAR3_T32COPY_ACCESS "RO" |
| #define M33_ID_ISAR3_TABBRANCH_ACCESS "RO" |
| #define M33_ID_ISAR3_TRUENOP_ACCESS "RO" |
| #define M33_ID_ISAR4_BARRIER_ACCESS "RO" |
| #define M33_ID_ISAR4_PSR_M_ACCESS "RO" |
| #define M33_ID_ISAR4_SYNCPRIM_FRAC_ACCESS "RO" |
| #define M33_ID_ISAR4_UNPRIV_ACCESS "RO" |
| #define M33_ID_ISAR4_WITHSHIFTS_ACCESS "RO" |
| #define M33_ID_ISAR4_WRITEBACK_ACCESS "RO" |
| #define M33_ID_ISAR5_ACCESS "RW" |
| #define M33_ID_MMFR0_AUXREG_ACCESS "RO" |
| #define M33_ID_MMFR0_OUTERSHR_ACCESS "RO" |
| #define M33_ID_MMFR0_PMSA_ACCESS "RO" |
| #define M33_ID_MMFR0_SHARELVL_ACCESS "RO" |
| #define M33_ID_MMFR0_TCM_ACCESS "RO" |
| #define M33_ID_MMFR1_ACCESS "RW" |
| #define M33_ID_MMFR2_WFISTALL_ACCESS "RO" |
| #define M33_ID_MMFR3_BPMAINT_ACCESS "RO" |
| #define M33_ID_MMFR3_CMAINTSW_ACCESS "RO" |
| #define M33_ID_MMFR3_CMAINTVA_ACCESS "RO" |
| #define M33_ID_PFR0_STATE0_ACCESS "RO" |
| #define M33_ID_PFR0_STATE1_ACCESS "RO" |
| #define M33_ID_PFR1_MPROGMOD_ACCESS "RO" |
| #define M33_ID_PFR1_SECURITY_ACCESS "RO" |
| #define M33_INT_ATREADY_AFVALID_ACCESS "RO" |
| #define M33_INT_ATREADY_ATREADY_ACCESS "RO" |
| #define M33_INT_ATVALID_AFREADY_ACCESS "RW" |
| #define M33_INT_ATVALID_ATREADY_ACCESS "RW" |
| #define M33_ITCHIN_CTCHIN_ACCESS "RO" |
| #define M33_ITCHOUT_CTCHOUT_ACCESS "RW" |
| #define M33_ITCTRL_IME_ACCESS "RW" |
| #define M33_ITM_CIDR0_PRMBL_0_ACCESS "RO" |
| #define M33_ITM_CIDR1_CLASS_ACCESS "RO" |
| #define M33_ITM_CIDR1_PRMBL_1_ACCESS "RO" |
| #define M33_ITM_CIDR2_PRMBL_2_ACCESS "RO" |
| #define M33_ITM_CIDR3_PRMBL_3_ACCESS "RO" |
| #define M33_ITM_DEVARCH_ARCHITECT_ACCESS "RO" |
| #define M33_ITM_DEVARCH_ARCHPART_ACCESS "RO" |
| #define M33_ITM_DEVARCH_ARCHVER_ACCESS "RO" |
| #define M33_ITM_DEVARCH_PRESENT_ACCESS "RO" |
| #define M33_ITM_DEVARCH_REVISION_ACCESS "RO" |
| #define M33_ITM_DEVTYPE_MAJOR_ACCESS "RO" |
| #define M33_ITM_DEVTYPE_SUB_ACCESS "RO" |
| #define M33_ITM_ITCTRL_IME_ACCESS "RW" |
| #define M33_ITM_PIDR0_PART_0_ACCESS "RO" |
| #define M33_ITM_PIDR1_DES_0_ACCESS "RO" |
| #define M33_ITM_PIDR1_PART_1_ACCESS "RO" |
| #define M33_ITM_PIDR2_DES_1_ACCESS "RO" |
| #define M33_ITM_PIDR2_JEDEC_ACCESS "RO" |
| #define M33_ITM_PIDR2_REVISION_ACCESS "RO" |
| #define M33_ITM_PIDR3_CMOD_ACCESS "RO" |
| #define M33_ITM_PIDR3_REVAND_ACCESS "RO" |
| #define M33_ITM_PIDR4_DES_2_ACCESS "RO" |
| #define M33_ITM_PIDR4_SIZE_ACCESS "RO" |
| #define M33_ITM_PIDR5_ACCESS "RW" |
| #define M33_ITM_PIDR6_ACCESS "RW" |
| #define M33_ITM_PIDR7_ACCESS "RW" |
Copyright (c) 2024 Raspberry Pi Ltd.
SPDX-License-Identifier: BSD-3-Clause
| #define M33_ITM_STIM0_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM10_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM11_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM12_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM13_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM14_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM15_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM16_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM17_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM18_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM19_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM1_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM20_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM21_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM22_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM23_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM24_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM25_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM26_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM27_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM28_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM29_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM2_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM30_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM31_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM3_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM4_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM5_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM6_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM7_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM8_STIMULUS_ACCESS "RW" |
| #define M33_ITM_STIM9_STIMULUS_ACCESS "RW" |
| #define M33_ITM_TCR_BUSY_ACCESS "RO" |
| #define M33_ITM_TCR_GTSFREQ_ACCESS "RW" |
| #define M33_ITM_TCR_ITMENA_ACCESS "RW" |
| #define M33_ITM_TCR_STALLENA_ACCESS "RW" |
| #define M33_ITM_TCR_SWOENA_ACCESS "RW" |
| #define M33_ITM_TCR_SYNCENA_ACCESS "RW" |
| #define M33_ITM_TCR_TRACEBUSID_ACCESS "RW" |
| #define M33_ITM_TCR_TSENA_ACCESS "RW" |
| #define M33_ITM_TCR_TSPRESCALE_ACCESS "RW" |
| #define M33_ITM_TCR_TXENA_ACCESS "RW" |
| #define M33_ITM_TER0_STIMENA_ACCESS "RW" |
| #define M33_ITM_TPR_PRIVMASK_ACCESS "RW" |
| #define M33_ITTRIGOUT_CTTRIGOUT_ACCESS "RW" |
| #define M33_MMFAR_ADDRESS_ACCESS "RW" |
| #define M33_MPU_CTRL_ENABLE_ACCESS "RW" |
| #define M33_MPU_CTRL_HFNMIENA_ACCESS "RW" |
| #define M33_MPU_CTRL_PRIVDEFENA_ACCESS "RW" |
| #define M33_MPU_MAIR0_ATTR0_ACCESS "RW" |
| #define M33_MPU_MAIR0_ATTR1_ACCESS "RW" |
| #define M33_MPU_MAIR0_ATTR2_ACCESS "RW" |
| #define M33_MPU_MAIR0_ATTR3_ACCESS "RW" |
| #define M33_MPU_MAIR1_ATTR4_ACCESS "RW" |
| #define M33_MPU_MAIR1_ATTR5_ACCESS "RW" |
| #define M33_MPU_MAIR1_ATTR6_ACCESS "RW" |
| #define M33_MPU_MAIR1_ATTR7_ACCESS "RW" |
| #define M33_MPU_RBAR_A1_AP_ACCESS "RW" |
| #define M33_MPU_RBAR_A1_BASE_ACCESS "RW" |
| #define M33_MPU_RBAR_A1_SH_ACCESS "RW" |
| #define M33_MPU_RBAR_A1_XN_ACCESS "RW" |
| #define M33_MPU_RBAR_A2_AP_ACCESS "RW" |
| #define M33_MPU_RBAR_A2_BASE_ACCESS "RW" |
| #define M33_MPU_RBAR_A2_SH_ACCESS "RW" |
| #define M33_MPU_RBAR_A2_XN_ACCESS "RW" |
| #define M33_MPU_RBAR_A3_AP_ACCESS "RW" |
| #define M33_MPU_RBAR_A3_BASE_ACCESS "RW" |
| #define M33_MPU_RBAR_A3_SH_ACCESS "RW" |
| #define M33_MPU_RBAR_A3_XN_ACCESS "RW" |
| #define M33_MPU_RBAR_AP_ACCESS "RW" |
| #define M33_MPU_RBAR_BASE_ACCESS "RW" |
| #define M33_MPU_RBAR_SH_ACCESS "RW" |
| #define M33_MPU_RBAR_XN_ACCESS "RW" |
| #define M33_MPU_RLAR_A1_ATTRINDX_ACCESS "RW" |
| #define M33_MPU_RLAR_A1_EN_ACCESS "RW" |
| #define M33_MPU_RLAR_A1_LIMIT_ACCESS "RW" |
| #define M33_MPU_RLAR_A2_ATTRINDX_ACCESS "RW" |
| #define M33_MPU_RLAR_A2_EN_ACCESS "RW" |
| #define M33_MPU_RLAR_A2_LIMIT_ACCESS "RW" |
| #define M33_MPU_RLAR_A3_ATTRINDX_ACCESS "RW" |
| #define M33_MPU_RLAR_A3_EN_ACCESS "RW" |
| #define M33_MPU_RLAR_A3_LIMIT_ACCESS "RW" |
| #define M33_MPU_RLAR_ATTRINDX_ACCESS "RW" |
| #define M33_MPU_RLAR_EN_ACCESS "RW" |
| #define M33_MPU_RLAR_LIMIT_ACCESS "RW" |
| #define M33_MPU_RNR_REGION_ACCESS "RW" |
| #define M33_MPU_TYPE_DREGION_ACCESS "RO" |
| #define M33_MPU_TYPE_SEPARATE_ACCESS "RO" |
| #define M33_MVFR0_FPDIVIDE_ACCESS "RO" |
| #define M33_MVFR0_FPDP_ACCESS "RO" |
| #define M33_MVFR0_FPROUND_ACCESS "RO" |
| #define M33_MVFR0_FPSP_ACCESS "RO" |
| #define M33_MVFR0_FPSQRT_ACCESS "RO" |
| #define M33_MVFR0_SIMDREG_ACCESS "RO" |
| #define M33_MVFR1_FMAC_ACCESS "RO" |
| #define M33_MVFR1_FPDNAN_ACCESS "RO" |
| #define M33_MVFR1_FPFTZ_ACCESS "RO" |
| #define M33_MVFR1_FPHP_ACCESS "RO" |
| #define M33_MVFR2_FPMISC_ACCESS "RO" |
| #define M33_NSACR_CP0_ACCESS "RW" |
| #define M33_NSACR_CP10_ACCESS "RW" |
| #define M33_NSACR_CP11_ACCESS "RW" |
| #define M33_NSACR_CP1_ACCESS "RW" |
| #define M33_NSACR_CP2_ACCESS "RW" |
| #define M33_NSACR_CP3_ACCESS "RW" |
| #define M33_NSACR_CP4_ACCESS "RW" |
| #define M33_NSACR_CP5_ACCESS "RW" |
| #define M33_NSACR_CP6_ACCESS "RW" |
| #define M33_NSACR_CP7_ACCESS "RW" |
| #define M33_NVIC_IABR0_ACTIVE_ACCESS "RW" |
| #define M33_NVIC_IABR1_ACTIVE_ACCESS "RW" |
| #define M33_NVIC_ICER0_CLRENA_ACCESS "RW" |
| #define M33_NVIC_ICER1_CLRENA_ACCESS "RW" |
| #define M33_NVIC_ICPR0_CLRPEND_ACCESS "RW" |
| #define M33_NVIC_ICPR1_CLRPEND_ACCESS "RW" |
| #define M33_NVIC_IPR0_PRI_N0_ACCESS "RW" |
| #define M33_NVIC_IPR0_PRI_N1_ACCESS "RW" |
| #define M33_NVIC_IPR0_PRI_N2_ACCESS "RW" |
| #define M33_NVIC_IPR0_PRI_N3_ACCESS "RW" |
| #define M33_NVIC_IPR10_PRI_N0_ACCESS "RW" |
| #define M33_NVIC_IPR10_PRI_N1_ACCESS "RW" |
| #define M33_NVIC_IPR10_PRI_N2_ACCESS "RW" |
| #define M33_NVIC_IPR10_PRI_N3_ACCESS "RW" |
| #define M33_NVIC_IPR11_PRI_N0_ACCESS "RW" |
| #define M33_NVIC_IPR11_PRI_N1_ACCESS "RW" |
| #define M33_NVIC_IPR11_PRI_N2_ACCESS "RW" |
| #define M33_NVIC_IPR11_PRI_N3_ACCESS "RW" |
| #define M33_NVIC_IPR12_PRI_N0_ACCESS "RW" |
| #define M33_NVIC_IPR12_PRI_N1_ACCESS "RW" |
| #define M33_NVIC_IPR12_PRI_N2_ACCESS "RW" |
| #define M33_NVIC_IPR12_PRI_N3_ACCESS "RW" |
| #define M33_NVIC_IPR13_PRI_N0_ACCESS "RW" |
| #define M33_NVIC_IPR13_PRI_N1_ACCESS "RW" |
| #define M33_NVIC_IPR13_PRI_N2_ACCESS "RW" |
| #define M33_NVIC_IPR13_PRI_N3_ACCESS "RW" |
| #define M33_NVIC_IPR14_PRI_N0_ACCESS "RW" |
| #define M33_NVIC_IPR14_PRI_N1_ACCESS "RW" |
| #define M33_NVIC_IPR14_PRI_N2_ACCESS "RW" |
| #define M33_NVIC_IPR14_PRI_N3_ACCESS "RW" |
| #define M33_NVIC_IPR15_PRI_N0_ACCESS "RW" |
| #define M33_NVIC_IPR15_PRI_N1_ACCESS "RW" |
| #define M33_NVIC_IPR15_PRI_N2_ACCESS "RW" |
| #define M33_NVIC_IPR15_PRI_N3_ACCESS "RW" |
| #define M33_NVIC_IPR1_PRI_N0_ACCESS "RW" |
| #define M33_NVIC_IPR1_PRI_N1_ACCESS "RW" |
| #define M33_NVIC_IPR1_PRI_N2_ACCESS "RW" |
| #define M33_NVIC_IPR1_PRI_N3_ACCESS "RW" |
| #define M33_NVIC_IPR2_PRI_N0_ACCESS "RW" |
| #define M33_NVIC_IPR2_PRI_N1_ACCESS "RW" |
| #define M33_NVIC_IPR2_PRI_N2_ACCESS "RW" |
| #define M33_NVIC_IPR2_PRI_N3_ACCESS "RW" |
| #define M33_NVIC_IPR3_PRI_N0_ACCESS "RW" |
| #define M33_NVIC_IPR3_PRI_N1_ACCESS "RW" |
| #define M33_NVIC_IPR3_PRI_N2_ACCESS "RW" |
| #define M33_NVIC_IPR3_PRI_N3_ACCESS "RW" |
| #define M33_NVIC_IPR4_PRI_N0_ACCESS "RW" |
| #define M33_NVIC_IPR4_PRI_N1_ACCESS "RW" |
| #define M33_NVIC_IPR4_PRI_N2_ACCESS "RW" |
| #define M33_NVIC_IPR4_PRI_N3_ACCESS "RW" |
| #define M33_NVIC_IPR5_PRI_N0_ACCESS "RW" |
| #define M33_NVIC_IPR5_PRI_N1_ACCESS "RW" |
| #define M33_NVIC_IPR5_PRI_N2_ACCESS "RW" |
| #define M33_NVIC_IPR5_PRI_N3_ACCESS "RW" |
| #define M33_NVIC_IPR6_PRI_N0_ACCESS "RW" |
| #define M33_NVIC_IPR6_PRI_N1_ACCESS "RW" |
| #define M33_NVIC_IPR6_PRI_N2_ACCESS "RW" |
| #define M33_NVIC_IPR6_PRI_N3_ACCESS "RW" |
| #define M33_NVIC_IPR7_PRI_N0_ACCESS "RW" |
| #define M33_NVIC_IPR7_PRI_N1_ACCESS "RW" |
| #define M33_NVIC_IPR7_PRI_N2_ACCESS "RW" |
| #define M33_NVIC_IPR7_PRI_N3_ACCESS "RW" |
| #define M33_NVIC_IPR8_PRI_N0_ACCESS "RW" |
| #define M33_NVIC_IPR8_PRI_N1_ACCESS "RW" |
| #define M33_NVIC_IPR8_PRI_N2_ACCESS "RW" |
| #define M33_NVIC_IPR8_PRI_N3_ACCESS "RW" |
| #define M33_NVIC_IPR9_PRI_N0_ACCESS "RW" |
| #define M33_NVIC_IPR9_PRI_N1_ACCESS "RW" |
| #define M33_NVIC_IPR9_PRI_N2_ACCESS "RW" |
| #define M33_NVIC_IPR9_PRI_N3_ACCESS "RW" |
| #define M33_NVIC_ISER0_SETENA_ACCESS "RW" |
| #define M33_NVIC_ISER1_SETENA_ACCESS "RW" |
| #define M33_NVIC_ISPR0_SETPEND_ACCESS "RW" |
| #define M33_NVIC_ISPR1_SETPEND_ACCESS "RW" |
| #define M33_NVIC_ITNS0_ITNS_ACCESS "RW" |
| #define M33_NVIC_ITNS1_ITNS_ACCESS "RW" |
| #define M33_PIDR0_PART_0_ACCESS "RO" |
| #define M33_PIDR1_DES_0_ACCESS "RO" |
| #define M33_PIDR1_PART_1_ACCESS "RO" |
| #define M33_PIDR2_DES_1_ACCESS "RO" |
| #define M33_PIDR2_JEDEC_ACCESS "RO" |
| #define M33_PIDR2_REVISION_ACCESS "RO" |
| #define M33_PIDR3_CMOD_ACCESS "RO" |
| #define M33_PIDR3_REVAND_ACCESS "RO" |
| #define M33_PIDR4_DES_2_ACCESS "RO" |
| #define M33_PIDR4_SIZE_ACCESS "RO" |
| #define M33_PIDR5_ACCESS "RW" |
| #define M33_PIDR6_ACCESS "RW" |
| #define M33_PIDR7_ACCESS "RW" |
| #define M33_SAU_CTRL_ALLNS_ACCESS "RW" |
| #define M33_SAU_CTRL_ENABLE_ACCESS "RW" |
| #define M33_SAU_RBAR_BADDR_ACCESS "RW" |
| #define M33_SAU_RLAR_ENABLE_ACCESS "RW" |
| #define M33_SAU_RLAR_LADDR_ACCESS "RW" |
| #define M33_SAU_RLAR_NSC_ACCESS "RW" |
| #define M33_SAU_RNR_REGION_ACCESS "RW" |
| #define M33_SAU_TYPE_SREGION_ACCESS "RO" |
| #define M33_SCR_SEVONPEND_ACCESS "RW" |
| #define M33_SCR_SLEEPDEEP_ACCESS "RW" |
| #define M33_SCR_SLEEPDEEPS_ACCESS "RW" |
| #define M33_SCR_SLEEPONEXIT_ACCESS "RW" |
| #define M33_SFAR_ADDRESS_ACCESS "RW" |
| #define M33_SFSR_AUVIOL_ACCESS "RW" |
| #define M33_SFSR_INVEP_ACCESS "RW" |
| #define M33_SFSR_INVER_ACCESS "RW" |
| #define M33_SFSR_INVIS_ACCESS "RW" |
| #define M33_SFSR_INVTRAN_ACCESS "RW" |
| #define M33_SFSR_LSERR_ACCESS "RW" |
| #define M33_SFSR_LSPERR_ACCESS "RW" |
| #define M33_SFSR_SFARVALID_ACCESS "RW" |
| #define M33_SHCSR_BUSFAULTACT_ACCESS "RW" |
| #define M33_SHCSR_BUSFAULTENA_ACCESS "RW" |
| #define M33_SHCSR_BUSFAULTPENDED_ACCESS "RW" |
| #define M33_SHCSR_HARDFAULTACT_ACCESS "RW" |
| #define M33_SHCSR_HARDFAULTPENDED_ACCESS "RW" |
| #define M33_SHCSR_MEMFAULTACT_ACCESS "RW" |
| #define M33_SHCSR_MEMFAULTENA_ACCESS "RW" |
| #define M33_SHCSR_MEMFAULTPENDED_ACCESS "RW" |
| #define M33_SHCSR_MONITORACT_ACCESS "RW" |
| #define M33_SHCSR_NMIACT_ACCESS "RW" |
| #define M33_SHCSR_PENDSVACT_ACCESS "RW" |
| #define M33_SHCSR_SECUREFAULTACT_ACCESS "RW" |
| #define M33_SHCSR_SECUREFAULTENA_ACCESS "RW" |
| #define M33_SHCSR_SECUREFAULTPENDED_ACCESS "RW" |
| #define M33_SHCSR_SVCALLACT_ACCESS "RW" |
| #define M33_SHCSR_SVCALLPENDED_ACCESS "RW" |
| #define M33_SHCSR_SYSTICKACT_ACCESS "RW" |
| #define M33_SHCSR_USGFAULTACT_ACCESS "RW" |
| #define M33_SHCSR_USGFAULTENA_ACCESS "RW" |
| #define M33_SHCSR_USGFAULTPENDED_ACCESS "RW" |
| #define M33_SHPR1_PRI_4_3_ACCESS "RW" |
| #define M33_SHPR1_PRI_5_3_ACCESS "RW" |
| #define M33_SHPR1_PRI_6_3_ACCESS "RW" |
| #define M33_SHPR1_PRI_7_3_ACCESS "RW" |
| #define M33_SHPR2_PRI_10_ACCESS "RO" |
| #define M33_SHPR2_PRI_11_3_ACCESS "RW" |
| #define M33_SHPR2_PRI_8_ACCESS "RO" |
| #define M33_SHPR2_PRI_9_ACCESS "RO" |
| #define M33_SHPR3_PRI_12_3_ACCESS "RW" |
| #define M33_SHPR3_PRI_13_ACCESS "RO" |
| #define M33_SHPR3_PRI_14_3_ACCESS "RW" |
| #define M33_SHPR3_PRI_15_3_ACCESS "RW" |
| #define M33_STIR_INTID_ACCESS "RW" |
| #define M33_SYST_CALIB_NOREF_ACCESS "RO" |
| #define M33_SYST_CALIB_SKEW_ACCESS "RO" |
| #define M33_SYST_CALIB_TENMS_ACCESS "RO" |
| #define M33_SYST_CSR_CLKSOURCE_ACCESS "RW" |
| #define M33_SYST_CSR_COUNTFLAG_ACCESS "RO" |
| #define M33_SYST_CSR_ENABLE_ACCESS "RW" |
| #define M33_SYST_CSR_TICKINT_ACCESS "RW" |
| #define M33_SYST_CVR_CURRENT_ACCESS "RW" |
| #define M33_SYST_RVR_RELOAD_ACCESS "RW" |
| #define M33_TRCAUTHSTATUS_NSID_ACCESS "RO" |
| #define M33_TRCAUTHSTATUS_NSNID_ACCESS "RO" |
| #define M33_TRCAUTHSTATUS_SID_ACCESS "RO" |
| #define M33_TRCAUTHSTATUS_SNID_ACCESS "RO" |
| #define M33_TRCCCCTLR_THRESHOLD_ACCESS "RW" |
| #define M33_TRCCIDR0_PRMBL_0_ACCESS "RO" |
| #define M33_TRCCIDR1_CLASS_ACCESS "RO" |
| #define M33_TRCCIDR1_PRMBL_1_ACCESS "RO" |
| #define M33_TRCCIDR2_PRMBL_2_ACCESS "RO" |
| #define M33_TRCCIDR3_PRMBL_3_ACCESS "RO" |
| #define M33_TRCCLAIMCLR_CLR0_ACCESS "RW" |
| #define M33_TRCCLAIMCLR_CLR1_ACCESS "RW" |
| #define M33_TRCCLAIMCLR_CLR2_ACCESS "RW" |
| #define M33_TRCCLAIMCLR_CLR3_ACCESS "RW" |
| #define M33_TRCCLAIMSET_SET0_ACCESS "RW" |
| #define M33_TRCCLAIMSET_SET1_ACCESS "RW" |
| #define M33_TRCCLAIMSET_SET2_ACCESS "RW" |
| #define M33_TRCCLAIMSET_SET3_ACCESS "RW" |
| #define M33_TRCCNTRLDVR0_VALUE_ACCESS "RW" |
| #define M33_TRCCONFIGR_BB_ACCESS "RW" |
| #define M33_TRCCONFIGR_CCI_ACCESS "RW" |
| #define M33_TRCCONFIGR_COND_ACCESS "RW" |
| #define M33_TRCCONFIGR_RS_ACCESS "RW" |
| #define M33_TRCCONFIGR_TS_ACCESS "RW" |
| #define M33_TRCDEVARCH_ARCHID_ACCESS "RO" |
| #define M33_TRCDEVARCH_ARCHITECT_ACCESS "RO" |
| #define M33_TRCDEVARCH_PRESENT_ACCESS "RO" |
| #define M33_TRCDEVARCH_REVISION_ACCESS "RO" |
| #define M33_TRCDEVID_ACCESS "RW" |
| #define M33_TRCDEVTYPE_MAJOR_ACCESS "RO" |
| #define M33_TRCDEVTYPE_SUB_ACCESS "RO" |
| #define M33_TRCEVENTCTL0R_SEL0_ACCESS "RW" |
| #define M33_TRCEVENTCTL0R_SEL1_ACCESS "RW" |
| #define M33_TRCEVENTCTL0R_TYPE0_ACCESS "RW" |
| #define M33_TRCEVENTCTL0R_TYPE1_ACCESS "RW" |
| #define M33_TRCEVENTCTL1R_ATB_ACCESS "RW" |
| #define M33_TRCEVENTCTL1R_INSTEN0_ACCESS "RW" |
| #define M33_TRCEVENTCTL1R_INSTEN1_ACCESS "RW" |
| #define M33_TRCEVENTCTL1R_LPOVERRIDE_ACCESS "RW" |
| #define M33_TRCIDR0_COMMOPT_ACCESS "RO" |
| #define M33_TRCIDR0_CONDTYPE_ACCESS "RO" |
| #define M33_TRCIDR0_INSTP0_ACCESS "RO" |
| #define M33_TRCIDR0_NUMEVENT_ACCESS "RO" |
| #define M33_TRCIDR0_QFILT_ACCESS "RO" |
| #define M33_TRCIDR0_QSUPP_ACCESS "RO" |
| #define M33_TRCIDR0_RES1_ACCESS "RO" |
| #define M33_TRCIDR0_RETSTACK_ACCESS "RO" |
| #define M33_TRCIDR0_TRCBB_ACCESS "RO" |
| #define M33_TRCIDR0_TRCCCI_ACCESS "RO" |
| #define M33_TRCIDR0_TRCCOND_ACCESS "RO" |
| #define M33_TRCIDR0_TRCDATA_ACCESS "RO" |
| #define M33_TRCIDR0_TRCEXDATA_ACCESS "RO" |
| #define M33_TRCIDR0_TSSIZE_ACCESS "RO" |
| #define M33_TRCIDR10_NUMP1KEY_ACCESS "RO" |
| #define M33_TRCIDR11_NUMP1SPC_ACCESS "RO" |
| #define M33_TRCIDR12_NUMCONDKEY_ACCESS "RO" |
| #define M33_TRCIDR13_NUMCONDSPC_ACCESS "RO" |
| #define M33_TRCIDR1_DESIGNER_ACCESS "RO" |
| #define M33_TRCIDR1_RES1_ACCESS "RO" |
| #define M33_TRCIDR1_REVISION_ACCESS "RO" |
| #define M33_TRCIDR1_TRCARCHMAJ_ACCESS "RO" |
| #define M33_TRCIDR1_TRCARCHMIN_ACCESS "RO" |
| #define M33_TRCIDR2_CCSIZE_ACCESS "RO" |
| #define M33_TRCIDR2_CIDSIZE_ACCESS "RO" |
| #define M33_TRCIDR2_DASIZE_ACCESS "RO" |
| #define M33_TRCIDR2_DVSIZE_ACCESS "RO" |
| #define M33_TRCIDR2_IASIZE_ACCESS "RO" |
| #define M33_TRCIDR2_VMIDSIZE_ACCESS "RO" |
| #define M33_TRCIDR3_CCITMIN_ACCESS "RO" |
| #define M33_TRCIDR3_EXLEVEL_NS_ACCESS "RO" |
| #define M33_TRCIDR3_EXLEVEL_S_ACCESS "RO" |
| #define M33_TRCIDR3_NOOVERFLOW_ACCESS "RO" |
| #define M33_TRCIDR3_NUMPROC_ACCESS "RO" |
| #define M33_TRCIDR3_STALLCTL_ACCESS "RO" |
| #define M33_TRCIDR3_SYNCPR_ACCESS "RO" |
| #define M33_TRCIDR3_SYSSTALL_ACCESS "RO" |
| #define M33_TRCIDR3_TRCERR_ACCESS "RO" |
| #define M33_TRCIDR4_NUMACPAIRS_ACCESS "RO" |
| #define M33_TRCIDR4_NUMCIDC_ACCESS "RO" |
| #define M33_TRCIDR4_NUMDVC_ACCESS "RO" |
| #define M33_TRCIDR4_NUMPC_ACCESS "RO" |
| #define M33_TRCIDR4_NUMRSPAIR_ACCESS "RO" |
| #define M33_TRCIDR4_NUMSSCC_ACCESS "RO" |
| #define M33_TRCIDR4_NUMVMIDC_ACCESS "RO" |
| #define M33_TRCIDR4_SUPPDAC_ACCESS "RO" |
| #define M33_TRCIDR5_ATBTRIG_ACCESS "RO" |
| #define M33_TRCIDR5_LPOVERRIDE_ACCESS "RO" |
| #define M33_TRCIDR5_NUMCNTR_ACCESS "RO" |
| #define M33_TRCIDR5_NUMEXTIN_ACCESS "RO" |
| #define M33_TRCIDR5_NUMEXTINSEL_ACCESS "RO" |
| #define M33_TRCIDR5_NUMSEQSTATE_ACCESS "RO" |
| #define M33_TRCIDR5_REDFUNCNTR_ACCESS "RO" |
| #define M33_TRCIDR5_TRACEIDSIZE_ACCESS "RO" |
| #define M33_TRCIDR6_ACCESS "RW" |
| #define M33_TRCIDR7_ACCESS "RW" |
| #define M33_TRCIDR8_MAXSPEC_ACCESS "RO" |
| #define M33_TRCIDR9_NUMP0KEY_ACCESS "RO" |
| #define M33_TRCIMSPEC_SUPPORT_ACCESS "RO" |
| #define M33_TRCITATBIDR_ID_ACCESS "RW" |
| #define M33_TRCITIATBINR_AFVALIDM_ACCESS "RW" |
| #define M33_TRCITIATBINR_ATREADYM_ACCESS "RW" |
| #define M33_TRCITIATBOUTR_AFREADY_ACCESS "RW" |
| #define M33_TRCITIATBOUTR_ATVALID_ACCESS "RW" |
| #define M33_TRCPDCR_PU_ACCESS "RW" |
| #define M33_TRCPDSR_OSLK_ACCESS "RO" |
| #define M33_TRCPDSR_POWER_ACCESS "RO" |
| #define M33_TRCPDSR_STICKYPD_ACCESS "RO" |
| #define M33_TRCPIDR0_PART_0_ACCESS "RO" |
| #define M33_TRCPIDR1_DES_0_ACCESS "RO" |
| #define M33_TRCPIDR1_PART_0_ACCESS "RO" |
| #define M33_TRCPIDR2_DES_0_ACCESS "RO" |
| #define M33_TRCPIDR2_JEDEC_ACCESS "RO" |
| #define M33_TRCPIDR2_REVISION_ACCESS "RO" |
| #define M33_TRCPIDR3_CMOD_ACCESS "RO" |
| #define M33_TRCPIDR3_REVAND_ACCESS "RO" |
| #define M33_TRCPIDR4_DES_2_ACCESS "RO" |
| #define M33_TRCPIDR4_SIZE_ACCESS "RO" |
| #define M33_TRCPIDR5_ACCESS "RW" |
| #define M33_TRCPIDR6_ACCESS "RW" |
| #define M33_TRCPIDR7_ACCESS "RW" |
| #define M33_TRCPRGCTLR_EN_ACCESS "RW" |
| #define M33_TRCRSCTLR2_GROUP_ACCESS "RW" |
| #define M33_TRCRSCTLR2_INV_ACCESS "RW" |
| #define M33_TRCRSCTLR2_PAIRINV_ACCESS "RW" |
| #define M33_TRCRSCTLR2_SELECT_ACCESS "RW" |
| #define M33_TRCRSCTLR3_GROUP_ACCESS "RW" |
| #define M33_TRCRSCTLR3_INV_ACCESS "RW" |
| #define M33_TRCRSCTLR3_PAIRINV_ACCESS "RW" |
| #define M33_TRCRSCTLR3_SELECT_ACCESS "RW" |
| #define M33_TRCSSCSR_DA_ACCESS "RO" |
| #define M33_TRCSSCSR_DV_ACCESS "RO" |
| #define M33_TRCSSCSR_INST_ACCESS "RO" |
| #define M33_TRCSSCSR_PC_ACCESS "RO" |
| #define M33_TRCSSCSR_STATUS_ACCESS "RW" |
| #define M33_TRCSSPCICR_PC_ACCESS "RW" |
| #define M33_TRCSTALLCTLR_INSTPRIORITY_ACCESS "RO" |
| #define M33_TRCSTALLCTLR_ISTALL_ACCESS "RW" |
| #define M33_TRCSTALLCTLR_LEVEL_ACCESS "RW" |
| #define M33_TRCSTATR_IDLE_ACCESS "RO" |
| #define M33_TRCSTATR_PMSTABLE_ACCESS "RO" |
| #define M33_TRCSYNCPR_PERIOD_ACCESS "RO" |
| #define M33_TRCTSCTLR_SEL0_ACCESS "RW" |
| #define M33_TRCTSCTLR_TYPE0_ACCESS "RW" |
| #define M33_TRCVICTLR_EXLEVEL_S0_ACCESS "RW" |
| #define M33_TRCVICTLR_EXLEVEL_S3_ACCESS "RW" |
| #define M33_TRCVICTLR_SEL0_ACCESS "RW" |
| #define M33_TRCVICTLR_SSSTATUS_ACCESS "RW" |
| #define M33_TRCVICTLR_TRCERR_ACCESS "RW" |
| #define M33_TRCVICTLR_TRCRESET_ACCESS "RW" |
| #define M33_TRCVICTLR_TYPE0_ACCESS "RW" |
| #define M33_VTOR_TBLOFF_ACCESS "RW" |